Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package

ABSTRACT

A microelectronic package includes first and second encapsulated microelectronic elements, each of which includes a semiconductor die having a front face and contacts thereon. An encapsulant contacts at least an edge surface of each semiconductor die and extends in at least one lateral direction therefrom. Electrically conductive elements extend from the contacts and over the front face to locations overlying the encapsulant. The first and second microelectronic elements are affixed to one another such that one of the front or back surfaces of one of the first and second semiconductor dies is oriented towards one of the front or back surfaces of the other of the first and second semiconductor dies. A plurality of electrically conductive interconnects extend through the encapsulants of the first and second microelectronic elements and are electrically connected with at least one semiconductor die of the first and second microelectronic elements by the conductive elements.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. application Ser. No.13/563,085, filed on Jul. 31, 2012, now U.S. Pat. No. 9,391,008.

BACKGROUND OF THE INVENTION

The subject matter of the present application relates to microelectronicpackages and assemblies incorporating microelectronic packages.

Semiconductor chips are commonly provided as individual, prepackagedunits. A standard chip has a flat, rectangular body with a large frontface having contacts connected to the internal circuitry of the chip.Each individual chip typically is contained in a package having externalterminals which, in turn, are electrically connected to a circuit panelsuch as a printed circuit board and which connects the contacts of thechip to conductors of the circuit panel. In many conventional designs,the chip package occupies an area of the circuit panel considerablylarger than the area of the chip itself. As used in this disclosure withreference to a flat chip having a front face, the “area of the chip”should be understood as referring to the area of the front face.

Microelectronic packages may be fabricated at the wafer level; that is,the enclosure, terminations and other features that constitute thepackage, are fabricated while the chips, or die, are still in a waferform. After the die have been formed, the wafer is subject to a numberof additional process steps to form the package structure on the wafer,and the wafer is then diced to free the individually packaged die. Waferlevel processing may be a preferred fabrication method because it mayprovide a cost savings advantage, and because the footprint of each diepackage may be made identical, or nearly identical, to the size of thedie itself, resulting in very efficient utilization of area on theprinted circuit board to which the packaged die is attached. A diepackaged in this manner is commonly referred to as wafer-level chipscale package or wafer-level chip sized package (WLCSP).

In order to save additional space on the substrate to which a packageddie is mounted, multiple chips may be combined in a single package byvertically stacking them. Each die in the stack must typically providean electrical connection mechanism to either one or more other die inthe stack, or to the substrate on which the stack is mounted, or toboth. This allows the vertically stacked multiple die package to occupya surface area on a substrate that is less than the total surface areaof all the chips in the package added together. Such arrangements have,however, required the chips to be offset at least somewhat to provideaccess to the contacts of the upper chips for electrical connectionthereto, as the routing for all of the multiple chips is done along thesame surface of the package. This can also lead to complicated routingand for different paths to externally-connected logic between chips ofthe same package.

In light of the foregoing, certain improvements in multi-chipmicroelectronic packages can be made in order to improve electricalperformance, particularly in assemblies which include such packagesinterconnected with one another or other packages.

SUMMARY OF THE INVENTION

An aspect of the present disclosure relates to a microelectronicpackage. The microelectronic package includes first and secondencapsulated microelectronic elements, each of which includes asemiconductor die having a front face extending in first and secondlateral directions, a plurality of contacts on the front face, a backface opposite the front face, and an edge surface extending between thefront and back faces. An encapsulant contacts at least the edge surfaceof the semiconductor die and extends in at least one of the lateraldirections from the edge surface. Electrically conductive elementsextend from the contacts of the semiconductor die and over the frontface in at least one of the lateral directions to locations overlyingthe encapsulant. The first and second microelectronic elements areaffixed to one another such that one of the front or back surfaces ofone of the first and second semiconductor dies is oriented towards andadjacent to one of the front or back surfaces of the other of the firstand second semiconductor dies. The encapsulants of the first and secondmicroelectronic elements define respective outwardly opposite surfaces.The package further includes a plurality of electrically conductiveinterconnects extending through the encapsulants of the first and secondmicroelectronic elements. At least some of the conductive interconnectsare electrically connected with at least one semiconductor die of thefirst and second microelectronic elements by the conductive elements.The conductive interconnects are exposed at the outwardly oppositesurfaces.

In an example, the first and second microelectronic elements can beaffixed to one another such that the front faces of the first and secondsemiconductor dies confront one another. In another arrangement, thefirst and second microelectronic elements can be affixed to one anothersuch that the front face of the second semiconductor die confronts theback face of the first semiconductor die. In yet another example, thefirst and second microelectronic elements can be affixed to one anothersuch that the back faces of the first and second semiconductor diesconfront one another.

At least one of the microelectronic elements can be configured such thatthe major surface of the encapsulant is co-planar with the front face ofthe respective semiconductor die. Similarly, at least one of themicroelectronic elements can be configured such that the second majorsurface of the encapsulant is co-planar with the back face of thecorresponding semiconductor die.

The conductive interconnects can include laser-etched openings extendingbetween the outwardly opposite surfaces of the encapsulants andintersecting respective conductive elements, the openings being at leastpartially filled with a conductive metal. First ones of the conductiveinterconnects can be electrically connected with the first semiconductordie by respective conductive elements, and second ones of the conductiveinterconnects can be electrically connected with the secondsemiconductor die by respective conductive elements. In a particularexample, a quantity of the first conductive interconnects can be equalto a quantity of the second conductive interconnects. Further, all ofthe conductive interconnects can be either first conductiveinterconnects or second conductive interconnects.

In an example, the first and second semiconductor dies can be memorychips having a greater number of active devices configured to providememory storage array function than any other function. Each of thememory chips can include a dynamic random access memory (DRAM) storagearray.

A microelectronic assembly can include a first microelectronic packageaccording to the above description and a second microelectronic package.The second microelectronic package can define a first surface havingterminals exposed thereon and a second surface having package contactsexposed thereon. The second microelectronic package can further includea microelectronic element disposed between the first and second surfaceand electrically connected with terminals and the package contacts. Aplurality of conductive joining elements can be joined betweenconfronting ends of the conductive interconnects of the firstmicroelectronic package and the terminals of the second microelectronicpackage.

The microelectronic element of the second package can be a logic chiphaving a greater number of active devices configured to provide logicfunction than any other function. The second microelectronic package canfurther include a substrate on which the microelectronic element ismounted. The substrate can include conductive elements electricallyconnected between the microelectronic element and the terminals.

The terminals of the second package can be ends of wire bonds havingbases joined to respective ones of the conductive elements. In such anexample, the second microelectronic package can further include anencapsulation layer formed over a surface of the substrate and over atleast a portion of the microelectronic element. The encapsulation layercan further extend along edge surfaces of the wire bonds and canseparate the wire bonds. The encapsulation layer can define the firstsurface of the second package, and the end surfaces of the wire bondscan be uncovered by the encapsulation layer on the second surfacethereof.

In an example, first ones of the conductive interconnects can beelectrically connected with the first microelectronic element byrespective conductive elements, second ones of the conductiveinterconnects that can be electrically connected with the secondmicroelectronic element by respective conductive elements, and thirdones of the conductive interconnects that can be connected with neitherof the first or second microelectronic elements. The firstmicroelectronic package can further include a third microelectronicpackage overlying the first microelectronic package and having packagecontacts joined with the ends of the third conductive elements that areexposed on the first surface of the encapsulants.

In an exemplary configuration the second microelectronic package caninclude a substrate defining the first surface of the second package andhaving third surface opposite the first surface, the microelectronicelement being mounted on the third surface.

A system can include comprising the microelectronic assembly describedabove and one or more electronic components.

Another aspect of the present disclosure relates to a microelectronicpackage including first and second encapsulated microelectronicelements. Each microelectronic element includes a semiconductor diehaving a front face extending in first and second lateral directions, aplurality of contacts on the front face, a back face opposite the frontface, and an edge surface extending between the front and back faces.Each microelectronic element further has an encapsulant contacting atleast the edge surface of the respective semiconductor die and extendingin at least one of the lateral directions from the edge surface so as todefine a major surface coplanar with or parallel to the front face ofthe semiconductor die, and electrically conductive elements includingmetallized vias extending from the contacts of the semiconductor die andalong the front face. At least some of the conductive elements extendbeyond the edge surface to locations overlying the major surface of theencapsulant. The first and second microelectronic elements are affixedto one another such that the front faces confront one another and themajor surfaces confront one another. The package further includes aplurality of electrically conductive interconnects extending through theencapsulants of the first and second microelectronic elements in adirection away from the major surfaces. At least some of the conductiveinterconnects are electrically connected with at least one semiconductordie of the first and second microelectronic elements by the conductiveelements. The conductive interconnects are exposed at first and secondopposed surfaces of the encapsulants which are opposite the majorsurfaces.

Another aspect of the present disclosure relates to a method for makinga microelectronic package. The method includes forming a plurality ofelectrically conductive interconnects through first and secondencapsulated microelectronic elements. Each of the microelectronicelements includes a semiconductor die having a front face extending infirst and second lateral directions, a plurality of contacts on thefront face, a back face opposite the front face, and an edge surfaceextending between the front and back faces. An encapsulant contacts atleast the edge surface of the respective semiconductor die and extendsin at least one of the lateral directions from the edge surface.Electrically conductive elements extend from the contacts of thesemiconductor die in at least one of the lateral directions to locationsoverlying the encapsulant. The first and second microelectronic elementsare affixed to one another such that one of the front or back surfacesof one of the first and second semiconductor dies is oriented towardsand adjacent to one of the front or back surfaces of the other of thefirst and second semiconductor dies. The encapsulants of the first andsecond microelectronic elements define respective outwardly oppositesurfaces. The conductive interconnects are formed through theencapsulants of the first and second microelectronic elements such thatat least some of the conductive interconnects are electrically connectedwith at least one semiconductor die of the first and secondmicroelectronic by the conductive elements. The conductive interconnectsare exposed at the outwardly opposite surfaces.

The conductive interconnects can be formed by laser etching openingsthrough the encapsulants of the first and second microelectronicelements and through respective ones of the conductive elements and byat least partially filling the openings with a conductive metal.

In an example, method can further including affixing the first andsecond microelectronic elements to one another such that the front facesconfront one another. In another example, the method can further includeaffixing the first and second microelectronic elements to one anothersuch that the front face of the second microelectronic element confrontsthe back face of the first microelectronic element. In yet anotherexample, the method can further include affixing the first and secondmicroelectronic elements to one another such that the back facesconfront one another.

The conductive interconnects can be formed to include first conductiveinterconnects that are connected by respective conductive elements tothe first microelectronic element and second conductive interconnectsthat are connected by respective conductive elements to the secondmicroelectronic element. A quantity of first conductive interconnectsformed in the package can be equal to a quantity of second conductivevias formed in the package. The conductive interconnects can be furtherformed to include third conductive interconnects that are free fromother electrical connections within the package.

The method can further include forming the electrically conductiveelements that extend along a dielectric region overlying the respectivefront faces of the semiconductor dies and the first major surfaces ofthe encapsulants. Forming the electrically conductive elements caninclude forming the conductive elements on at least one of the first orsecond microelectronic elements prior affixing the microelectronicelements together. Additionally or alternatively, forming theelectrically conductive elements can include forming the conductiveelements on a dielectric region overlying at least one of the first orsecond microelectronic elements before affixing the microelectronicelements together.

Another aspect of the present disclosure relates to a method for makinga microelectronic assembly. The method includes making a firstmicroelectronic package by a steps including forming a plurality ofelectrically conductive interconnects through first and secondencapsulated microelectronic elements. Each of the microelectronicelements includes a semiconductor die having a front face extending infirst and second lateral directions, a plurality of contacts on thefront face, a back face opposite the front face, and an edge surfaceextending between the front and back faces. An encapsulant contacts atleast the edge surface of the respective semiconductor die and extendsin at least one of the lateral directions from the edge surface.Electrically conductive elements including metalized vias extend fromthe contacts of the semiconductor die in at least one of the lateraldirections to locations overlying the encapsulant. The first and secondmicroelectronic elements are affixed to one another such that one of thefront or back surfaces of one of the first and second semiconductor diesis oriented towards and adjacent to one of the front or back surfaces ofthe other of the first and second semiconductor dies. The encapsulantsof the first and second microelectronic elements define respectiveoutwardly opposite surfaces. The conductive interconnects are formedthrough the encapsulants of the first and second microelectronicelements such that at least some of the conductive interconnects areelectrically connected with at least one semiconductor die of the firstand second microelectronic by the conductive elements. The conductiveinterconnects are exposed at the outwardly opposite surfaces. The methodfurther includes positioning the first microelectronic package over asecond microelectronic package including a logic chip electricallyconnected with terminals exposed on a first surface of the secondpackage and package contacts exposed on a second surface of the secondmicroelectronic package. The method further includes joining ends of theconductive interconnects of the first microelectronic package that facethe second microelectronic package with the terminals of the secondmicroelectronic package using a plurality of conductive joiningelements.

The method can further include positioning a third microelectronicpackage over the first microelectronic package, the thirdmicroelectronic package including terminals exposed on a surface thereofthat is positioned to confront the first package. In such an example,the method can further include joining terminals of the thirdmicroelectronic package with ends of the conductive interconnects thatare disposed toward the third microelectronic package.

The conductive interconnects can be formed to include first conductiveinterconnects connected by respective conductive elements to the firstmicroelectronic element, second conductive interconnects connected byrespective conductive elements to the second microelectronic element,and third conductive interconnects that are free from other electricalconnections within the package. The terminals of the thirdmicroelectronic package can be joined with ends of the third conductiveinterconnects, the third conductive interconnects electricallyconnecting the third package to the second package.

BRIEF DESCRIPTION OF THE DRAWINGS

Various embodiments of the present invention will be now described withreference to the appended drawings. It is appreciated that thesedrawings depict only some embodiments of the invention and are thereforenot to be considered limiting of its scope.

FIG. 1 shows a microelectronic assembly according to an embodiment ofthe present disclosure;

FIG. 1A shows a detail view of a microelectronic package included in theassembly of FIG. 1;

FIG. 2 shows a top plan view of the package of FIG. 1;

FIG. 3 shows a bottom plan view of the package of FIG. 1;

FIG. 4 shows a microelectronic assembly according to a furtherembodiment of the present disclosure;

FIG. 5 shows a microelectronic assembly according to a furtherembodiment of the present disclosure;

FIGS. 6-10 show various iterations of an in-process unit during methodsteps for making a microelectronic element according to anotherembodiment of the present disclosure;

FIG. 11 shows a microelectronic assembly according to another embodimentof the present disclosure;

FIG. 12 shows a microelectronic assembly according to another embodimentof the present disclosure; and

FIG. 13 shows a system that can include a microelectronic assemblyaccording to various embodiments of the present disclosure.

DETAILED DESCRIPTION

Turning now to the figures, where similar numeric references are used toindicate similar features, there is shown in FIG. 1 a microelectronicassembly 10 in the form a first microelectronic package 12 stacked overa second microelectronic package 50. In an example, assembly 10 can bein the form of a memory-on-logic assembly in which first package 12 is amemory package and second package 50 is a logic package, although thearrangements described herein can be used in arrangements with packagesof different types or combinations of different types. Both first 12 andsecond 50 packages include one or more respective semiconductor dies 18and 26 that themselves include a plurality of active devices. A memorypackage can be a package with semiconductor dies that have a majority ofactive devices configured for a memory storage array function.Similarly, a logic package can be one in which a majority of the activedevices therein are configured to execute processor functions.

First microelectronic package 12 can include first and secondencapsulated microelectronic elements 14 and 16. Each of theencapsulated microelectronic elements 14, 16 includes a semiconductordie 18. As mentioned above, these semiconductor dies 18 can be in theform of memory chips such as DRAM chips or the like. In other examples,the semiconductor dies 18 can be in the form of application-specificintegrated circuit (ASIC) chips. Various combinations of ASIC and memorychips are also possible within package 12. Semiconductor die 18 furtherincludes a front face 20 that extends in lateral directions and haselement contacts 26 exposed thereon. A back face 22 is positionedopposite front face 20 and is generally parallel thereto. Edge surfaces24 extend between front face 20 and back face 22 defining an outerperiphery of die 18.

An encapsulant 28 at least partially surrounds semiconductor die 18.Encapsulant can be made from a dielectric material and can be molded orotherwise formed at least partially around die 18. Encapsulant 28 cancontact one or more edge surfaces 24 of die 18 and can extend awaytherefrom in one or more lateral directions normal to the edge surfaces24. In an example, front face 20 and back face 22 can be rectangular orsquare and four corresponding edge surfaces 24 can extend betweenrespective sides of front and back faces 20,22. Encapsulant 28 cansurround all four edge surfaces 24 and can extend away therefrom to givethe microelectronic element 14 or 16 a rectangular shape. Encapsulant 18includes first and second major surfaces 30 and 32 that are respectivelyassociated with and parallel to front and back faces 20 and 22 of thesemiconductor die 18. In some examples, encapsulant 28 can furthercontact back face 22 and extend away therefrom such that second majorsurface 32 overlies back face 32. In other embodiments, such as thatshown in FIG. 1, front and back faces 20 and 22 can be uncovered byencapsulant 28 such that first major surface 30 extends substantiallyco-planar with front face 20 and/or second major surface 32 extendssubstantially co-planar with back face 22.

Each microelectronic element 14 and 16 can further include a dielectricregion 48 overlying at least the front faces 20 of the semiconductordies 18. As seen in FIG. 1A, the dielectric region 48 may extend beyondthe edge surface 24 of the semiconductor die 18 to overlie first majorsurface 30 of the encapsulant 28. The dielectric region 48 may be partlyor entirely made of any suitable dielectric material. For example, thedielectric region 48 may comprise a layer of flexible material, such asa layer of polyimide, BT resin or other dielectric material of thecommonly used for making tape automated bonding (“TAB”) tapes.Alternatively, the dielectric region 48 may comprise a relatively rigid,board like material such as a thick layer of fiber-reinforced epoxy,such as, Fr-4 or Fr-5 board. Regardless of the material employed, thedielectric region 30 may include a single layer or multiple layers ofdielectric material.

As shown in the detail view of FIG. 1A, conductive elements can beconnected with the contacts 26 of the semiconductor dies 18.Specifically, conductive vias 38 can extend through dielectric region 48to connect with contacts 26 of semiconductor die 18. Additionalconductive features such as traces 36 can connect with the conductivevias 38 and can extend away therefrom in one or more lateral directionsalong dielectric region 48 over face 20 and can further over first majorsurface 30 of encapsulant 28 to connect with one or more contacts 26that can be positioned at various locations along first major surface30. Such conductive element can be made from a conductive metal such ascopper, gold, silver, nickel, aluminum, or various alloys thereof.

As further shown in FIG. 1A, first microelectronic element 14 and secondmicroelectronic package 16 can be assembled together such that the frontfaces 22 of the respective semiconductor dies 18 confront one another.In such an arrangement the first major surfaces 30 of the respectiveencapsulants 28 can confront each other as well. Microelectronicelements can be joined together by a bonding layer 44 that can be anadhesive, a molded dielectric, or the like that can be bonded betweenthe dielectric regions 48 of the microelectronic elements 14 and 16.Bonding layer 44 can be further configured to surround and insulateconductive elements, such as traces 36 and contacts 40. In the exampleshown, bonding layer 44 spaces apart microelectronic element 14 and 16such that the routing patterns of the traces 18 do not interfere withone another. In other examples, the routing patterns of the respectivefirst and second microelectronic elements 14,16 can be structured to belaterally spaced apart from each other such that the microelectronicelements 14 and 16 can be spaced closer together.

Conductive interconnects 40 can extend through the encapsulants 28 ofboth first and second microelectronic element 14 and 16 such that endsurfaces 46A thereof are exposed on the second major surfaces 32 of theencapsulant 28 of first microelectronic element 14 and opposite endsurfaces 46B are exposed on the second major surface 32 of theencapsulant 28 of second microelectronic element 16. Conductiveinterconnects 40 can also extend through and connect with respectiveones of the conductive elements associated with either of themicroelectronic elements 14 and 16. In the example of FIG. 1A,conductive element 40A connects with a pad 34 at the end of a trace 36that extends along major surface 30 and front face 20 of microelectronicelement 14 and connects to a respective contact of the semiconductor die18 of microelectronic element 14. Similarly, conductive element 40Bconnects with a pad 34 at the end of another trace 36 that extends alongmajor surface 30 and front face 20 of microelectronic element 16 andconnects to a respective contact 26 of the semiconductor die 18 ofmicroelectronic element 16. By this arrangement a number of connectionscan be made between the second major surfaces 32 of the microelectronicelements 14 and 16 and either semiconductor die 18. This can allow, forexample, connection to the semiconductor dies 18 of both microelectronicelements 14 and 16 by ends 46B of the conductive interconnections 40that are exposed at second major surface 32 of microelectronic element16 or vice versa. Conductive interconnects can be metalized vias thatare formed by plating a conductive metal into an opening that can beformed through the encapsulants and through portions of conductiveelements disposed therebetween by etching, drilling or the like, as willbe described in further detail below. Conductive metals forinterconnects 40 can include copper, gold, silver, nickel, aluminum orvarious alloys thereof.

Conductive interconnects 40 can be arranged in any configuration orpattern within encapsulants 28. In the example shown in FIG. 2,conductive interconnects 40 are arranged in an area array pattern inwhich interconnects 40 are laid out in a grid pattern of various rowsand columns of interconnects 40 within encapsulants 18 and surroundingsemiconductor dies 18. The interconnects 40 within such an array can bespaced apart from one another according to a pitch of the array that canbe less than, for example 500 microns and in another examples betweenabout 250 and 300 microns. The array can be configured to align with anarray of terminals 58 in second package 50, for example, to facilitate aparticular electrical connection between packages by joining terminals58 with, for example, ends 46B of conductive interconnects 40. This canallow for connection between, for example microelectronic element 52 andthe semiconductor dies 18 of both microelectronic elements 14 and 16 infirst package 12.

The conductive elements of the respective microelectronic elements 14and 16 can be arranged such that only a single contact 26 on one of thesemiconductor dies 18 is connected with a corresponding conductiveinterconnect 40. For example, the pads 34 of the respectivemicroelectronic elements 14 and 16 can be arranged in different arraysor other pattern that each partially corresponds to the array ofconductive interconnects 40. Such partially corresponding patterns canbe different as between microelectronic elements 14 and 16 such thatnone of the pads 34 associated with microelectronic element 14 occupy aposition of a pad 34 associated with microelectronic element 16, andvice versa. Numerous configurations are possible for such differentpatterns. In one example, all of the pads 34 of microelectronic element16 can be positioned inside the array of pads 34 of microelectronicelement 14. In another example, the pads 34 of microelectronic element14 can alternate in an array with the pads 34 of microelectronic element16, with further arrangements being possible. Traces 36 can be routedsuch that they do not contact any features within package 12 other thana single pad 34 and a single contact 26 on a corresponding semiconductordie 18.

As mentioned previously, conductive interconnects 40 can be positionedto connect with terminals 29 of second package 50, which in an examplecan be a logic package. As shown in FIG. 1, second package 50 can be inthe form of a microelectronic element 52 carried on a substrate 54 withterminals 58 on a surface of an encapsulant that overlies substrate.Terminals 58 can be end surfaces of interconnects 56 that extend fromconductive elements that extend along a surface of the substrate 54 toconnect with microelectronic element 52 by, for example, conductivemasses 70. Interconnects can be in any of a number of configurations andcan include conductive pins or posts. In another example, interconnects56 can be in the form of wire bonds, as described in U.S. Pat. No.7,391,121 to Otremba, in U.S. Pat. App. Pub. No. 2005/0095835(describing a wedge-bonding procedure that can be considered a form ofwire bonding), and in commonly-assigned U.S. patent application Ser.Nos. 13/462,158; 13/404,408; 13/405,108; 13/405,125; and Ser. No.13/404,458, the disclosures of which are incorporated herein byreference in their entireties. Substrate 54 can include redistributionto connect package contacts exposed on the substrate 54 oppositeterminals 58 with microelectronic element 52 to facilitate connectionbetween assembly 10 and other microelectronic devices in amicroelectronic system. In an embodiment, package contacts 60 canconnect with terminals on a circuit panel or the like (not shown) byconductive joining masses. Such package contacts 60 can be arranged in apattern or array as shown in FIG. 3 and can be input and outputconnections for assembly 10.

As shown in FIG. 4 an additional package 12B can be stacked on top ofpackage 12A. Package 12B can be of a similar configuration as package12A, which itself is similar to package 12 described above with respectto FIGS. 1-3. In such an example, package 12A can be adapted tofacilitate an electrical connection between package 12B and package 50.To accomplish this, some of the conductive interconnects 40 withinpackage 12A can be unconnected with either of the semiconductor dies 18within package 12A. Such interconnects 40 can further be unconnectedwith any conductive elements, such as pads 34 or traces 36 withinpackage 12A. These unconnected interconnects 40 within package 12A canconnect with conductive interconnects 40 within package 12B, whichthemselves can be connected with either of the semiconductor dies 18therein in a manner similar to that discussed above with respect topackage 12 in FIG. 1A. In a further example, some of the conductiveinterconnects 40 within package 12B can themselves be unconnected witheither of the semiconductor dies 18 in package 12B and can, along withunconnected interconnects 40 within package 12A can facilitate anelectrical connection between package 50 and a still further package(not shown) stacked on top of package 12B. The uppermost package in sucha stacked arrangement can be similar to package 12A or 12B, as shown inFIG. 4 or can be another form of a packaged microelectronic element (ormicroelectronic elements) with contacts exposed at least on a surfacethat faces the conductive interconnects 40 of a package beneath it.

FIG. 5 shows an assembly 110 that is a variation of the assembly ofFIG. 1. In particular, assembly 110 includes a first package 112 that issimilar in construction to that of package 12 in FIGS. 1-3. Assembly 110further includes a second package 150 that is similar to package 50 inFIGS. 1-4 but is configured such that the ends 158 of the interconnects56 are disposed away from package 112 and act as contacts for connectionof assembly 110 with external components, such as a circuit panel or thelike. Accordingly, the contacts on substrate 154 opposite themicroelectronic element 152 act as terminals 160 to which the ends 146Bof the conductive interconnects 146 of package 112 are connected usingconductive joining masses 70 or the like. In such an arrangement,interconnects 156 can be in the form of encapsulated wire bonds, asdescribed above to achieve a fine-pitch for the contacts 160 that arethe ends of the interconnects 156. Redistribution through substrate 154(or layers thereof) can provide for the desired configuration ofterminals 158 to connect with conductive interconnects 140. Furtherpackages (not shown) can be included in the assembly 110 in a similarway to that described above with respect to FIG. 4.

FIGS. 6-10 show the various components of assembly 10 during steps offabrication thereof in a method according to an embodiment of thepresent disclosure. In particular, FIG. 6 shows first microelectronicelement 14 and second microelectronic element 16 prior to assemblytogether. Microelectronic elements 14 and 16 can be formed asreconstituted wafer-level packages. That is, they can be formed in awafer with a plurality of semiconductor dies that are embedded in anencapsulant layer. The wafer can then be diced or segmented intoindividual microelectronic elements including, for example, a singlesemiconductor die with a portion of the encapsulant surrounding at leasta portion thereof. Other process steps can be used to create theparticular package, including grinding one or more surfaces of theencapsulant to create major surfaces 30 and 32 that are flush with thefront 20 and back 22 faces of the semiconductor die 18, which themselvescan be thinned by such a grinding process. Before or after segmentation,the conductive elements, including the pads 34, traces 36 and conductivevias 38 can be formed along front face 20 of the semiconductor die 18and the first major surface 30 of the encapsulant 28 according to theprinciples discussed above. An additional dielectric layer canoptionally be formed over the portions of first major surface 30 andfront face 20 not covered by conductive elements.

As shown in FIG. 6, the microelectronic elements 14 and 16 can then bepositioned such that front faces 20 and first major surfaces 30 confrontone another with their respective conductive elements appropriatelypositioned with respect to each other as described above. Themicroelectronic elements 14 and 16 can then be bonded together by anadhesive layer or a curable dielectric material layer disposed betweenmicroelectronic elements 14 and 16. In some embodiments such a layer canintersperse between conductive elements when microelectronic elements 14and 16 are moved together. Such bonding can result in the in-processunit 12′ shown in FIG. 7.

The in-process unit of FIG. 7 can then be processed to form openingsthrough the encapsulants 28 of the first and second microelectronicelements 14 and 16 and through desired portions of the conductiveelements associated therewith. In an example, wherein the pads 34associated with microelectronic elements 14 and 16 are arranged in anarray when microelectronic elements 14 and 16 are assembled together,the openings 42 can be made through the pads 34 and the portions of theareas of the encapsulants 28 that overlie the pads 34. In the exampleshown, openings 42 can extend completely through in-process unit 12 suchthat they are open to second major surfaces 32 of both microelectronicelements 14 and 16. In other embodiments, such as when the package beingmade is intended as a topmost package in a stack the openings can extendfrom a single one of the second major surfaces 32 to a depth adequate toextend through the pads 34. Openings 42 can be made by drilling, etchingor the like. Etching can be done using a chemical etchant or the likewith a mask layer being at least temporarily over second major surfaces32. In another example, openings 42 can be formed by laser etching.Laser etching can be advantageous because it can usespecially-configured equipment that can locate and target the portionsof in-process unit 12′ for formation of holes 42 based on detection ofpads 34.

Openings 42 can then be filled with a conductive metal, such as copperor other metals discussed above, to form conductive interconnects 40.This can be done by plating the conductive metal into the holes. Suchplating can be done by electroplating or electroless plating and can bedone after depositing a seed layer or the like within openings 42. Whenused such a seed layer can be conductive to allow for electricalconnection between conductive interconnects 40 and pads 34 or otherconductive elements. In some embodiments, the ends 46 of the conductiveinterconnects 40 can be planarized by grinding or the like so that theybecome substantially flush with second major surfaces 32. In otherexamples, contacts can be formed over the ends 46 of the interconnects40 to provide additional area for connection to other components.

As shown in FIG. 10, package 12 is then aligned with package 50 suchthat the conductive interconnects 40, in particular the faces 46Bthereof, align with the desired terminals 58 of package 50. In oneexample, package 50 can be formed as a package including encapsulatedwire bond interconnects by any of the methods described inabove-referenced commonly-assigned U.S. patent application Ser. Nos.13/462,158; 13/404,408; 13/405,108; 13/405,125; and Ser. No. 13/404,458.Faces 46B of interconnects 40 are then joined with respective terminals58 using conductive joining masses 70 such as solder balls or the liketo form a package such as that shown in FIG. 1. Additional steps can beperformed, including the formation of additional packages that aresimilar to package 12 that can be further assembled over package 12 withthe conductive interconnects of such an additional package connectedwith certain ones of the conductive interconnects 40 of package 12, asdescribed above with respect to FIG. 4.

FIG. 11 shows a microelectronic assembly 210 that includes a package 212assembled with another microelectronic package 250, wherein package 250can be similar to package 50 discussed with respect to FIG. 1. Package212 can be a variation of package 12 shown in FIG. 1 with many commoncharacteristics. In particular, package 212 can include first and secondmicroelectronic elements 214 and 216 that include semiconductor dies 218with encapsulants 228 at least partially surrounding the semiconductordies 218. Each microelectronic element 214 and 216 can includerespective conductive elements including conductive vias 238 connectedwith contacts 226 of the respective semiconductor dies 218 and traces 36extending along the front faces 20 and the first major surfaces 30 topads 34. The first and second microelectronic elements 214 and 216 inthe embodiment shown in FIG. 11 can be assembled together such that thefirst major surface 230 of microelectronic element 214 confronts thesecond major surface 232 of microelectronic element 216. Further, insuch an arrangement front face 220 of the semiconductor die 218 of firstmicroelectronic element 214 confronts the back surface 222 of thesemiconductor die 218 of the second microelectronic element 216.

In the arrangement of FIG. 11, the locations of the conductive elements,in particular the pads 234 of the respective microelectronic packages214 and 216 can be determined in a similar way to those ofmicroelectronic package 12 of FIGS. 1-4. In particular, pads 234 can bepositioned such that each conductive interconnect 240 passes throughonly one pad 234 of only one of the microelectronic elements 214 or 216.Also, as in package 12 of FIGS. 1-4 some of the conductive interconnects240 can be free from electrical connections with either of thesemiconductor dies 218 within package 212 and can be used to connectanother package (not shown) stacked on top of package 212 with terminals258 of package 250.

The method of fabricating assembly 210 can also be similar to thefabrication method of assembly 10 as described in FIGS. 6-10 but withmicroelectronic elements 214 and 216 being positioned in theback-to-front arrangement described above when being assembled together.Further, the conductive elements of second microelectronic element 216can be formed after assembly thereof with first microelectronic element214.

FIG. 12 shows another variation of a microelectronic assembly 310 thatincludes a package 312 assembled with another microelectronic package350, wherein package 350 can be similar to package 50 discussed withrespect to FIG. 1. Package 312 can be a variation of package 12 shown inFIG. 1 with many common characteristics. In particular, package 312 caninclude first and second microelectronic elements 314 and 316 thatinclude semiconductor dies 318 with encapsulants 328 at least partiallysurrounding the semiconductor dies 318. Each microelectronic element 314and 316 can include respective conductive elements including conductivevias 338 connected with contacts 326 of the respective semiconductordies 318 and traces 336 extending along the front faces 320 and thefirst major surfaces 330 to pads 334. The first and secondmicroelectronic elements 314 and 316 in the embodiment shown in FIG. 12can be assembled together such that the second major surfaces 330 of themicroelectronic elements 214 and 216 confront each other. Further, insuch an arrangement the back faces 322 of the semiconductor dies 218 ofthe first and second microelectronic elements 214 and 216 can confronteach other.

In the arrangement of FIG. 12, the locations of the conductive elements,in particular the pads 334 of the respective microelectronic packages314 and 316 can be determined in a similar way to those ofmicroelectronic package 12 of FIGS. 1-4. In particular, pads 334 can bepositioned such that each conductive interconnect 340 passes throughonly one pad 334 of only one of the microelectronic elements 314 or 316.Also, as in package 12 of FIGS. 1-4 some of the conductive interconnects340 can be free from electrical connections with either of thesemiconductor dies 318 within package 312 and can be used to connectanother package (not shown) stacked on top of package 312 with terminals358 of package 350. In some variations of package 312 of FIG. 12,conductive pads 334 of second microelectronic element 316 are exposed onpackage 312 and confront terminals 358 of package 35 and, thus, can bedirectly connected therewith by solder balls 370 or the like.Accordingly, such pads 334 may not require any conductive interconnects340 to be associated therewith. In such an example, conductiveinterconnects 340 can connect with pads of first microelectronic element314 and can also be unconnected within package 312 for connection withadditional packages (not shown) assembled above package 312.

The method of fabricating assembly 310 can also be similar to thefabrication method of assembly 10 as described in FIGS. 6-10 but withmicroelectronic elements 314 and 316 being positioned in theback-to-back arrangement described above when being assembled together.Further, the conductive elements of first and second microelectronicelement 314 and 316 can be formed after being assembled together.

The structures discussed above can be utilized in construction ofdiverse electronic systems. For example, a system 1 in accordance with afurther embodiment of the invention includes microelectronic package 10,as described above with respect to FIGS. 1-4, in conjunction with otherelectronic components 2 and 3. In the example depicted, component 2 is asemiconductor chip whereas component 3 is a display screen, but anyother components can be used. Of course, although only two additionalcomponents are depicted in FIG. 13 for clarity of illustration, thesystem may include any number of such components. The microelectronicpackage 10 as described above may be, for example, a microelectronicpackage as discussed above in connection with FIG. 1, or a structureincorporating plural microelectronic packages as discussed withreference to FIG. 4. Package 10 can further include any one of theembodiments described in FIG. 11 or 12. In a further variant, multiplevariations may be provided, and any number of such structures may beused.

Microelectronic package 10 and components 2 and 3 are mounted in acommon housing 4, schematically depicted in broken lines, and areelectrically interconnected with one another as necessary to form thedesired circuit. In the exemplary system shown, the system includes acircuit panel 5 such as a flexible printed circuit board, and thecircuit panel includes numerous conductors 6, of which only one isdepicted in FIG. 13, interconnecting the components with one another.However, this is merely exemplary; any suitable structure for makingelectrical connections can be used.

The housing 4 is depicted as a portable housing of the type usable, forexample, in a cellular telephone or personal digital assistant, andscreen 3 is exposed at the surface of the housing. Where microelectronicpackage 10 includes a light-sensitive element such as an imaging chip, alens 7 or other optical device also may be provided for routing light tothe structure. Again, the simplified system shown in FIG. 13 is merelyexemplary; other systems, including systems commonly regarded as fixedstructures, such as desktop computers, routers and the like can be madeusing the structures discussed above.

Although the invention herein has been described with reference toparticular embodiments, it is to be understood that these embodimentsare merely illustrative of the principles and applications of thepresent invention. It is therefore to be understood that numerousmodifications may be made to the illustrative embodiments and that otherarrangements may be devised without departing from the spirit and scopeof the present invention as defined by the appended claims.

The invention claimed is:
 1. A method for making a microelectronicpackage, comprising: forming a plurality of electrically conductiveinterconnects through first and second encapsulated microelectronicelements, each of the microelectronic elements including: asemiconductor die having a front face extending in first and secondlateral directions, a plurality of contacts on the front face, a backface opposite the front face, and an edge surface extending between thefront and back faces; an encapsulant contacting at least the edgesurface of the respective semiconductor die and extending in at leastone of the lateral directions from the edge surface, the front face andthe back face of the respective semiconductor die being uncovered by theencapsulant; and electrically conductive elements extending from thecontacts of the semiconductor die in at least one of the lateraldirections to locations overlying the encapsulant; wherein the first andsecond microelectronic elements are affixed to one another by a bondinglayer of dielectric material that extends between and contactsdielectric material at confronting surfaces of the first and secondmicroelectronic elements such that one of the front or back surfaces ofone of the first and second semiconductor dies is oriented towards andadjacent to one of the front or back surfaces of the other of the firstand second semiconductor dies and at least some conductive elements ofat least one of the microelectronic elements are abutting the bondinglayer between the confronting surfaces, the encapsulants of the firstand second microelectronic elements defining first and second oppositeand outwardly facing surfaces, respectively, remote from the bondinglayer, the first outwardly facing surface extending substantiallyco-planar with the front face or the back face of the semiconductor dieof the first microelectronic element, and the second outwardly facingsurface extending substantially co-planar with the front face or theback face of the semiconductor die of the second microelectronicelement; and wherein the conductive interconnects are formed through theencapsulants of the first and second microelectronic elements, eachconductive interconnect extending through an opening having a continuousinterior surface extending from the first outwardly facing surfacethrough the encapsulant of the first microelectronic element, andthrough the bonding layer and the encapsulant of the secondmicroelectronic element to the second outwardly facing surface, whereinat least one of the conductive interconnects is electrically coupledwith at least one of the conductive elements at a location adjacent thebonding layer and thereby electrically connected with at least onesemiconductor die of the first and second microelectronic elements. 2.The method of claim 1, wherein the conductive interconnects are formedby laser etching the openings through the encapsulants of the first andsecond microelectronic elements and through respective ones of theconductive elements and by at least partially filling the openings witha conductive metal.
 3. The method of claim 1, further including affixingthe first and second microelectronic elements to one another such thatthe front faces confront one another.
 4. The method of claim 1, furtherincluding affixing the first and second microelectronic elements to oneanother such that the front face of the second microelectronic elementconfronts the back face of the first microelectronic element.
 5. Themethod of claim 1, further including affixing the first and secondmicroelectronic elements to one another such that the back facesconfront one another.
 6. The method of claim 1, wherein the conductiveinterconnects are formed to include first conductive interconnectsconnected by respective conductive elements to the first microelectronicelement and second conductive interconnects connected by respectiveconductive elements to the second microelectronic element.
 7. The methodof claim 6, wherein a quantity of first conductive interconnects formedin the package is equal to a quantity of second conductive vias formedin the package.
 8. A method for making a microelectronic package,comprising: forming a plurality of electrically conductive interconnectsthrough first and second encapsulated microelectronic elements, each ofthe microelectronic elements including: a semiconductor die having afront face extending in first and second lateral directions, a pluralityof contacts on the front face, a back face opposite the front face, andan edge surface extending between the front and back faces; anencapsulant contacting at least the edge surface of the respectivesemiconductor die and extending in at least one of the lateraldirections from the edge surface; and electrically conductive elementsextending from the contacts of the semiconductor die in at least one ofthe lateral directions to locations overlying the encapsulant; whereinthe first and second microelectronic elements are affixed to one anotherby a bonding layer of dielectric material that extends between andcontacts dielectric material at confronting surfaces of the first andsecond microelectronic elements such that one of the front or backsurfaces of one of the first and second semiconductor dies is orientedtowards and adjacent to one of the front or back surfaces of the otherof the first and second semiconductor dies and at least some conductiveelements of at least one of the microelectronic elements are abuttingthe bonding layer between the confronting surfaces, the encapsulants ofthe first and second microelectronic elements defining first and secondopposite and outwardly facing surfaces, respectively, remote from thebonding layer; and wherein the conductive interconnects are formedthrough the encapsulants of the first and second microelectronicelements, each conductive interconnect extending through an openinghaving a continuous interior surface extending from the first outwardlyfacing surface through the encapsulant of the first microelectronicelement, and through the bonding layer and the encapsulant of the secondmicroelectronic element to the second outwardly facing surface, whereinat least one of the conductive interconnects is electrically coupledwith at least one of the conductive elements at a location adjacent thebonding layer and thereby electrically connected with at least onesemiconductor die of the first and second microelectronic elements,wherein the conductive interconnects are formed to include firstconductive interconnects connected by respective conductive elements tothe first microelectronic element and second conductive interconnectsconnected by respective conductive elements to the secondmicroelectronic element, and wherein the conductive interconnects arefurther formed to include third conductive interconnects that are freefrom other electrical connections within the package.
 9. The method ofclaim 1, further including forming the electrically conductive elements.10. The method of claim 9, wherein forming the electrically conductiveelements includes forming the conductive elements on at least one of thefirst or second microelectronic elements prior to a step of affixing themicroelectronic elements together.
 11. The method of claim 9, whereinforming the electrically conductive elements includes forming theconductive elements on a dielectric region overlying at least one of thefirst or second microelectronic elements before a step of affixing themicroelectronic elements together.
 12. A method for making amicroelectronic assembly, comprising: making a first microelectronicpackage by a method including: forming a plurality of electricallyconductive interconnects through first and second encapsulatedmicroelectronic elements, each of the microelectronic elementsincluding: a semiconductor die having a front face extending in firstand second lateral directions, a plurality of contacts on the frontface, a back face opposite the front face, and an edge surface extendingbetween the front and back faces; an encapsulant contacting at least theedge surface of the respective semiconductor die and extending in atleast one of the lateral directions from the edge surface, the frontface and the back face of the respective semiconductor die beinguncovered by the encapsulant; and electrically conductive elementsincluding metalized vias extending from the contacts of thesemiconductor die in at least one of the lateral directions to locationsoverlying the encapsulant; wherein the first and second microelectronicelements are affixed to one another by a bonding layer of dielectricmaterial that extends between and contacts dielectric material atconfronting surfaces of the first and second microelectronic elementssuch that one of the front or back surfaces of one of the first andsecond semiconductor dies is oriented towards and adjacent to one of thefront or back surfaces of the other of the first and secondsemiconductor dies and at least some conductive elements of at least oneof the microelectronic elements are abutting the bonding layer betweenthe confronting surfaces, the encapsulants of the first and secondmicroelectronic elements defining first and second opposite andoutwardly facing surfaces, respectively, remote from the bonding layer,the first outwardly facing surface extending substantially co-planarwith the front face or the back face of the semiconductor die of thefirst microelectronic element, and the second outwardly facing surfaceextending substantially co-planar with the front face or the back faceof the semiconductor die of the second microelectronic element; andwherein the conductive interconnects are formed through the encapsulantsof the first and second microelectronic elements, each conductiveinterconnect extending through an opening having a continuous interiorsurface extending from the first outwardly facing surface through theencapsulant of the first microelectronic element, and through thebonding layer and the encapsulant of the second microelectronic elementto the second outwardly facing surface, wherein at least one of theconductive interconnects is electrically coupled with at least one ofthe conductive elements at a location adjacent the bonding layer andthereby electrically connected with at least one semiconductor die ofthe first and second microelectronic elements; positioning the firstmicroelectronic package over a second microelectronic package includinga logic chip electrically connected with terminals exposed on a firstsurface of the second package and package contacts exposed on a secondsurface of the second microelectronic package; and joining ends of theconductive interconnects of the first microelectronic package that facethe second microelectronic package with the terminals of the secondmicroelectronic package using a plurality of conductive joiningelements.
 13. The method of claim 12, further including positioning athird microelectronic package over the first microelectronic package,the third microelectronic package including terminals exposed on asurface thereof that is positioned to confront the first package, themethod further including joining terminals of the third microelectronicpackage with ends of the conductive interconnects that are disposedtoward the third microelectronic package.
 14. The method of claim 13,wherein the conductive interconnects are formed to include firstconductive interconnects connected by respective conductive elements tothe first microelectronic element, second conductive interconnectsconnected by respective conductive elements to the secondmicroelectronic element, and third conductive interconnects that arefree from other electrical connections within the first microelectronicpackage, the terminals of the third microelectronic package are joinedwith ends of the third conductive interconnects, the third conductiveinterconnects electrically connecting the third microelectronic packageto the second microelectronic package.